Methods of forming complementary-metal-oxide-semiconductor (CMOS) field effect transistors may include selectively forming p-channel transistors having silicon germanium (SiGe) source and drain regions within a silicon substrate. As illustrated by FIGS. 1A-1P, one conventional method includes forming a semiconductor substrate 10 having a plurality of electrically insulating trench isolation regions 14 therein. These trench isolation regions 14 are illustrated in FIG. 1A as separating semiconductor well regions of different conductivity type. These semiconductor well regions are illustrated as a P-well region 12a and an adjacent N-well region 12b. A gate electrode of an NMOS transistor and a gate electrode of a PMOS transistor are formed on the P-well region 12a and the N-well region 12b, respectively. The gate electrode of the NMOS transistor is illustrated as including a gate oxide layer 16a, a polysilicon gate layer 18a, a silicon nitride capping layer 22a and a separating oxide capping layer 20a. The gate electrode of the PMOS transistor is illustrated as including a gate oxide layer 16b, a polysilicon gate layer 18b, a silicon nitride capping layer 22b and a separating oxide capping layer 20b. An oxide layer 24, which may be formed as a thermal oxide layer having a non-uniform thickness, is formed on a surface of the substrate 10 and on the sidewalls and top surfaces of the gate electrodes.
Referring now to FIGS. 1B-1C, a silicon nitride layer 26 is conformally deposited on the substrate 10 and on the gate electrodes of the NMOS and PMOS transistors and then a patterned photoresist mask 28 is selectively formed on the P-well regions 12a to cover regions where the NMOS transistor(s) is to be formed. Exposed portions of the silicon nitride layer 26 are then selectively etched for a sufficient duration to expose the oxide layer 24 and define silicon nitride spacers 26a on sidewalls of the gate electrode of the PMOS transistor. Thereafter, as illustrated by FIGS. 1E-1F, the patterned photoresist mask 28 is removed to expose a patterned silicon nitride layer 26b. The silicon nitride spacers 26a and the patterned silicon nitride layer 26b (and trench isolation regions 14) are then used as an etching mask during a reactive ion etching (RIE) step. During this RIE step, source and drain region trenches 30 are formed in the N-well region 12b. Then, as illustrated by FIG. 1G, an epitaxial growth step is selectively performed to define silicon germanium (SiGe) source and drain regions 32 within the trenches 30. A step may then be performed to selectively remove silicon nitride from the intermediate structure of FIG. 1G. In particular, as illustrated by FIG. 1H, a hot phosphoric acid solution is used to selectively etch back the silicon nitride spacers 26a, the patterned silicon nitride layer 26b and the silicon nitride capping layer 22b. 
Thereafter, an electrically insulating layer 34 is conformally deposited on the intermediate structure of FIG. 1H. This electrically insulating layer may be a low temperature oxide (LTO) layer having a sufficient thickness to operate as sidewall spacers. In particular, a reactive ion etching (RIE) step may be performed to etch back the electrically insulating layer 34 to thereby define the sidewall spacers 34a and 34b, as illustrated by FIG. 1J. A patterned photoresist layer 36 is then formed to cover the P-well region 12a. As illustrated by FIGS. 1K-1M, the patterned photoresist layer 36 is then used as an implant mask during a step to form source/drain regions 37b and a halo implant region 39b within the N-well region 12b, by performing horizontal PMOS halo and source/drain implantation. During these steps, P-type source/drain dopants 37a are implanted into the N-well region 12b, using the gate electrode of the PMOS transistor and the sidewall spacers 34b as an implant mask. In addition, halo dopants 39a are implanted underneath the sidewall spacers 34b using a horizontal halo (i.e., high angle) implant step to define a halo region 39b, which inhibits short-channel effects within the PMOS transistor. The patterned photoresist layer 36 is then removed (e.g., stripped).
Similarly, as illustrated by FIGS. 1N-1P, a patterned photoresist layer 40 is then formed and used as an implant mask during a step to further define additional source/drain regions 37d and an additional halo implant region 39d within the N-well region 12b, by performing vertical PMOS halo and source/drain implantation. During these steps, P-type source/drain dopants 37c are implanted into the N-well region 12b, using the gate electrode of a PMOS transistor and the sidewall spacers 34b as an implant mask. In addition, halo dopants 39c are implanted underneath the sidewall spacers 34b using a vertical halo (i.e., high angle) implant step to define a halo region 39d, which inhibits short-channel effects within a PMOS transistor. The patterned photoresist layer 40 is then removed (e.g., stripped) and additional processing steps (not shown) as performed.